CLOCKSTEERING

Clock steering status

Platform:

OEM719, OEM729, OEM7500, OEM7600, OEM7700, OEM7720, PwrPak7, CPT7, CPT7700, SMART7, SMART2

The CLOCKSTEERING log is used to monitor the current state of the clock steering process. All oscillators have some inherent drift. By default the receiver attempts to steer the receiver clock to accurately match GPS reference time. If for some reason this is not desired, this behavior can be disabled using the CLOCKADJUST command.

If the CLOCKADJUST command is ENABLED and the receiver is configured to use an external reference frequency (set in the EXTERNALCLOCK command), then the clock steering process takes over the VARF output pins and may conflict with a previously entered EVENTOUTCONTROL command.

Message ID: 26

Log Type: Asynch

Recommended Input:

log clocksteeringa onchanged

ASCII Example:

#CLOCKSTEERINGA,USB1,0,64.0,FINESTEERING,2209,502647.507,02000020,0f61,16809;INTERNAL,SECOND_ORDER,11000,6888.960937500,0.029999999,0.621999979,0.357,-0.027*5368cd23

To configure the receiver to use an external reference oscillator, see the EXTERNALCLOCK command.

Field	Field type	Description	Format	Binary Bytes	Binary Offset
1	Log header	CLOCKSTEERING header For information about log headers, see ASCII, Abbreviated ASCII or Binary.		H	0
2	source	Clock source, see Table: Clock Source	Enum	4	H
3	steering state	Steering state, see Table: Steering State	Enum	4	H+4
4	period	Period of the pulse width modulated signal used to control the oscillator. This value is set using the CLOCKCALIBRATE command.	Ulong	4	H+8
5	pulse width	Current pulse width of the pulse width modulated signal used to control the oscillator. The starting point for this value is set using the CLOCKCALIBRATE command. The clock steering loop continuously adjusts this value in an attempt to drive the receiver clock offset and drift terms to zero.	Double	8	H+12
6	bandwidth	The current band width of the clock steering tracking loop in Hz. This value is set using the CLOCKCALIBRATE command.	Double	8	H+20
7	slope	The current clock drift change in m/s/bit for a 1 LSB pulse width. This value is set using the CLOCKCALIBRATE command.	Float	4	H+28
8	offset	The last valid receiver clock offset computed (m). It is the same as Field # 18 of the CLOCKMODEL log.	Double	8	H+32
9	drift rate	The last valid receiver clock drift rate received (m/s). It is the same as Field # 19 of the CLOCKMODEL log.	Double	8	H+40
10	xxxx	32-bit CRC (ASCII and Binary only)	Hex	4	H+48
11	[CR][LF]	Sentence terminator (ASCII only)	-	-	-

Clock Source
Binary	ASCII	Description
0	INTERNAL	The receiver is currently steering its internal VCTCXO using an internal VARF signal
1	EXTERNAL	The receiver is currently steering an external oscillator using the external VARF signal

Steering State
Binary	ASCII	Description
0	FIRST_ORDER	Upon start-up, the clock steering task adjusts the VARF pulse width to reduce the receiver clock drift rate to below 1 ms using a 1st order control loop. This is the normal start-up state of the clock steering loop.
1	SECOND_ORDER	Once the receiver has reduced the clock drift to below 1 m/s, it enters a second order control loop and attempts to reduce the receiver clock offset to zero. This is the normal runtime state of the clock steering process.
2	CALIBRATE_HIGH	This state corresponds to when the calibration process is measuring at the "High" pulse width setting. The CALIBRATE_HIGH state is only seen if you force the receiver to do a clock steering calibration using the CLOCKCALIBRATE command. With the CLOCKCALIBRATE command, you can force the receiver to calibrate the slope and center pulse width of the currently selected oscillator, to steer. The receiver measures the drift rate at several "High" and "Low" pulse width settings.
3	CALIBRATE_LOW	This state corresponds to when the calibration process is measuring at the "Low" pulse width setting. The CALIBRATE_LOW state is only seen if you force the receiver to do a clock steering calibration using the CLOCKCALIBRATE command. With the CLOCKCALIBRATE command, you can force the receiver to calibrate the slope and center pulse width of the currently selected oscillator, to steer. The receiver measures the drift rate at several "High" and "Low" pulse width settings.
4	CALIBRATE_CENTER	This state corresponds to the "Center" calibration process. Once the center has been found, the modulus pulse width, center pulse width, loop bandwidth and measured slope values are saved in NVM and are used from now on for the currently selected oscillator (INTERNAL or EXTERNAL). After the receiver has measured the "High" and "Low" pulse width setting, the calibration process enters a "Center calibration" process where it attempts to find the pulse width required to zero the clock drift rate.