CLOCKMODEL

Current clock model status

Platform:

OEM719, OEM729, OEM7500, OEM7600, OEM7700, OEM7720, PwrPak7, CPT7, CPT7700, SMART7, SMART2

The CLOCKMODEL log contains a filtered representation of the receiver's clock bias relative to GPS system time.

Message ID: 16

Log Type: Synch

Recommended Input:

log clockmodela ontime 1

ASCII Example:

#CLOCKMODELA,USB1,0,65.0,FINESTEERING,2209,502563.000,02000020,98f9,16809;
VALID,0,502563.000,502563.000,1.645927507e-01,-3.828977102e-02,0.000000000,
3.705045540e-02,8.770260153e-04,0.000000000,8.770260153e-04,3.242199713e-03,
0.000000000,0.000000000,0.000000000,0.000000000,0.227,-4.714598090e-02,FALSE
*6572f493

The CLOCKMODEL log can be used to monitor the clock drift of an internal oscillator once the CLOCKADJUST mode has been disabled. Watch the CLOCKMODEL log to see the drift rate and adjust the oscillator until the drift stops.

Field

Field type

Description

Format

Binary Bytes

Binary Offset

1

Log header

CLOCKMODEL header

For information about log headers, see ASCII, Abbreviated ASCII or Binary.

 

H

0

2

status

Clock model status. See Table: Clock Model Status

Enum

4

H

3

reject_count

Number of rejected instantaneous clock errors

Ulong

4

H+4

4

propagation_time

Time of last propagation

GPSec

4

H+8

5

update_time

Time of last update

GPSec

4

H+12

6

bias

Receiver clock bias (m)

Double

8

H+16

7

rate

Receiver clock bias rate (m/s)

Double

8

H+24

8

Reserved

Double

8

H+32

9

bias_variance

Receiver clock bias variance (m2)

Double

8

H+40

10

covariance

Receiver clock bias/bias rate covariance (m2/s)

Double

8

H+48

11

Reserved

Double

8

H+56

12

Reserved

Double

8

H+64

13

rate_variance

Receiver clock bias rate variance (m2/s2)

Double

8

H+72

14

Reserved

Double

8

H+80

15

Reserved

Double

8

H+88

16

Reserved

Double

8

H+96

17

Reserved

Double

8

H+104

18

instantaneous_bias

Last instantaneous receiver clock bias (m)

Double

8

H+112

19

instantaneous_rate

Last instantaneous receiver clock bias rate (m/s)

Double

8

H+120

20

Reserved

Bool

4

H+128

21

xxxx

32-bit CRC (ASCII and Binary only)

Hex

4

H+132

22

[CR][LF]

Sentence terminator (ASCII only)

-

-

-

Clock Model Status

Clock Status (Binary)

Clock Status (ASCII)

Description

0

VALID

The clock model is valid

1

CONVERGING

The clock model is near validity

2

ITERATING

The clock model is iterating towards validity

3

INVALID

The clock model is not valid